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I am a Senior Marketing Executive at Silicon Interfaces.
Silicon Interfaces offers on-site contract services and offshore turnkey =
projects development at our development centers. It has three main areas =
of activities - VLSI Design & Software Services and Esiliconworld.com. =
To augment its VLSI Design Center, the Company has Silicon Cores - the =
Core to the Intelligent SystemT an IP Development program =
(http://www.siliconinterfaces.com/AssetsIP.htm)
and the Silicon =
Institute of Technology =
(http://www.siliconinterfaces.com/CareersSIT.htm)
for imparting =
training.
VLSI Designs
Silicon Interfaces offers Designs Services in the areas Networking, =
Data Communications, Interconnect, Embedded and Storage, primarily in =
the areas of System Verilog/Verilog/VHDL/SystemC for Design, Modeling =
and Verification of complex SoC, ASIC and FPGAs. Apart from Front-end =
Digital Designs we also do work on Mixed-Mode, Analog and Backend =
Physical IC Layout and we offer a complete solution to our Customer. We =
also provide specialized EDA Product Sup****t Services. For more =
information on VLSI Design Services please visit =
http://www.siliconinterfaces.com/ServicesVLSI.htm
We have one very good Verification Engineer "SIVEA0508A" available =
currently on immediate basis who fit very well into your requirement. =
Perhaps if it would be of interest to you. His experience summary is as =
below:
Experience Summary: Total 6 years of experience including onsite =
experience (2 years) in Singa****e and Germany. Experienced in working on =
an IP, SOC and doing Chip/System Level Verification using 'e' language =
(3.5 years) and C. Extensive expert usage of Specman tool as well eRM =
and IPCM Methodologies. Worked on Verification by undertaking =
Constraint-Driven Test Generation with Data and Tem****al Checking and =
Functional Coverage Analysis. Developed eVC Components. Worked on DFT =
(Pattern Generation) related to Clock System and ADSL Modules. =
Generating Test Pattern for Wafer Level. Experienced on AMBA Interface. =
Key driver for the Cadence Canvas Conversations for paper titled =
"Resolving Verification challenges by leveraging Constraint Driven =
Verification using eRM" presented at Cadence CNDLive! Knowledge in all =
aspects of Design Life Cycle through Specification, Design Engineering, =
Modeling, Integration, Verification, Do***entation, including Code =
Do***entation and Maintenance.
Please revert to me at (408) 341 5330 if you would like to discuss this =
further.
Marketing Coordinator
Silicon Interfaces
a software and vlsi design center
Email: info@[EMAIL PROTECTED]
www.siliconinterfaces.com
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<DIV>
<DIV>
<DIV align=3Djustify><FONT face=3D"Book Antiqua" size=3D2>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN =
class=3Dtext1><SPAN=20
style=3D"FONT-SIZE: 9pt; FONT-FAMILY: 'Book Antiqua'"><FONT size=3D2>I =
am a Senior=20
Marketing Executive at <EM>Silicon =
Interfaces.</EM></FONT></SPAN></SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN =
class=3Dtext1><I=20
style=3D"mso-bidi-font-style: normal"><SPAN=20
style=3D"FONT-SIZE: 9pt; FONT-FAMILY: 'Book =
Antiqua'"></SPAN></I></SPAN> </P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN =
class=3Dtext1><I=20
style=3D"mso-bidi-font-style: normal"><SPAN=20
style=3D"FONT-SIZE: 9pt; FONT-FAMILY: 'Book Antiqua'">Silicon=20
Interfaces</SPAN></I></SPAN><SPAN class=3Dtext1><SPAN=20
style=3D"FONT-SIZE: 9pt; FONT-FAMILY: 'Book Antiqua'"> offers on-site =
contract=20
services and offshore turnkey projects development at our development =
centers.=20
It has three main areas of activities =96 VLSI Design & Software =
Services and=20
Esiliconworld.com. To augment its <?xml:namespace prefix =3D st1 ns =3D=20
"urn:schemas-microsoft-com:office:smarttags" /><st1:place=20
w:st=3D"on"><st1:PlaceName w:st=3D"on">VLSI</st1:PlaceName> =
<st1:PlaceName=20
w:st=3D"on">Design</st1:PlaceName> <st1:PlaceType=20
w:st=3D"on">Center</st1:PlaceType></st1:place>, the Company has Silicon =
Cores =96=20
the Core to the Intelligent System=99 an IP Development program (<A=20
href=3D"http://www.siliconinterfaces.com/AssetsIP.htm"><SPAN=20
style=3D"FONT-SIZE: 12pt"><FONT=20
color=3D#800080>http://www.siliconinterfaces.com/AssetsIP.htm</FONT></SPA=
N></A>)=20
and the Silicon Institute of Technology=20
(http://www.siliconinterfaces.com/CareersSIT.htm)
for imparting=20
training.</SPAN></SPAN><SPAN=20
style=3D"COLOR: black; FONT-FAMILY: 'Book Antiqua'"><BR=20
style=3D"mso-special-character: line-break"><BR=20
style=3D"mso-special-character: line-break"></P><?xml:namespace prefix =
=3D o ns =3D=20
"urn:schemas-microsoft-com:office:office" /><o:p></o:p></SPAN>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><B=20
style=3D"mso-bidi-font-weight: normal"><SPAN=20
style=3D"COLOR: black; FONT-FAMILY: 'Book Antiqua'"><FONT size=3D3>VLSI=20
Designs<o:p></o:p></FONT></SPAN></B></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><EM><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: red; FONT-FAMILY: 'Book =
Antiqua'">Silicon=20
Interfaces</SPAN></EM><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: 'Book Antiqua'"> offers Designs =
Services in=20
the areas <STRONG><SPAN style=3D"FONT-FAMILY: 'Book =
Antiqua'">Networking,=20
Data Communications, Interconnect, Embedded</SPAN></STRONG> and=20
<STRONG><SPAN style=3D"FONT-FAMILY: 'Book =
Antiqua'">Storage</SPAN></STRONG>,=20
primarily in the areas of <STRONG><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'">System=20
Verilog/Verilog/VHDL/SystemC</SPAN></STRONG> for Design, Modeling and=20
Verification of complex SoC, ASIC and FPGAs. Apart from <U>Front-end=20
Digital Designs</U> we also do work on <STRONG><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'">Mixed-Mode, Analog</SPAN></STRONG> =
and=20
<STRONG><SPAN style=3D"FONT-FAMILY: 'Book Antiqua'">Backend Physical IC=20
Layout</SPAN></STRONG> and we offer a complete solution to our Customer. =
We also=20
provide specialized <STRONG><SPAN style=3D"FONT-FAMILY: 'Book =
Antiqua'">EDA=20
Product Sup****t Services</SPAN></STRONG>. For more information on VLSI =
Design=20
Services please visit <A=20
href=3D"http://www.siliconinterfaces.com/ServicesVLSI.htm"><FONT=20
color=3D#800080>http://www.siliconinterfaces.com/ServicesVLSI.htm</FONT><=
/A></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"COLOR: black; FONT-FAMILY: 'Book =
Antiqua'"><EM></EM></SPAN> </P></SPAN></FONT></DIV>
<DIV align=3Djustify><FONT face=3D"Book Antiqua" size=3D2>We =
have one very good=20
Verification Engineer "SIVEA0508A" available currently on immediate =
basis who=20
fit very well into your requirement. Perhaps if it would be of interest =
to=20
you. His experience summary is as below:</FONT></DIV>
<DIV align=3Djustify><FONT face=3D"Book Antiqua" =
size=3D2></FONT> </DIV>
<DIV align=3Djustify><SPAN style=3D"FONT-FAMILY: 'Book Antiqua'"><FONT =
size=3D2><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'">Experience Summary: </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">Total</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'"> 6 years </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'">of =
</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'">experience </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book =
Antiqua'">including</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'"> onsite experience (2 years) in=20
</SPAN><st1:country-region><st1:place><SPAN=20
style=3D"FONT-FAMILY: 'Book =
Antiqua'">Singa****e</SPAN></st1:place></st1:country-region><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'"> and=20
</SPAN><st1:country-region><st1:place><SPAN=20
style=3D"FONT-FAMILY: 'Book =
Antiqua'">Germany</SPAN></st1:place></st1:country-region><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'">. </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">Experienced=20
</SPAN><SPAN style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: =
bold">in=20
working on an</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">=20
IP, SOC and doing Chip/System Level Verification </SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: =
bold">using</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">=20
=91e=92 language (3.5 years) and C. </SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: =
bold">Extensive expert=20
usage of</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">=20
Specman </SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: bold">tool =
as=20
well</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">=20
eRM and IPCM Methodologies. </SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-size: 9.0pt">Worked =
on=20
</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold; mso-bidi-font-size: =
9.0pt">Verification</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-size: 9.0pt"> by =
undertaking=20
</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold; mso-bidi-font-size: 9.0pt">Constraint-Driven =
Test Generation</SPAN><SPAN> with Data and Tem****al Checking</SPAN><SPAN =
style=3D"FONT-FAMILY: 'Book Antiqua'"> and </SPAN><SPAN>Functional =
Coverage=20
Analysis. Developed </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold; mso-bidi-font-size: 9.0pt">eVC</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-size: 9.0pt">=20
Components</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold; mso-bidi-font-size: 9.0pt">.=20
</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: bold; =
mso-bidi-font-size: 9.0pt">Worked=20
on </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold; mso-bidi-font-size: 9.0pt">DFT=20
(Pattern Generation) related to Clock System and ADSL Modules. =
Generating Test=20
Pattern for Wafer Level. </SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'">Experienced on </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book =
Antiqua'">AMBA</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'"> Interface. </SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: bold">Key =
driver for=20
the</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">=20
Cadence Canvas Conversations</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: bold"> for =
paper=20
titled "</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">Resolving=20
Verification challenges by leveraging Constraint Driven Verification =
using eRM"=20
</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'; mso-bidi-font-weight: =
bold">presented at=20
Cadence CNDLive! </SPAN><SPAN style=3D"FONT-FAMILY: 'Book =
Antiqua'">Knowledge in=20
all aspects of Design Life Cycle through </SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">Specification,=20
Design Engineering, Modeling, Integration, Verification</SPAN><SPAN=20
style=3D"FONT-FAMILY: 'Book Antiqua'">, Do***entation, including =
</SPAN><SPAN=20
style=3D"FONT-WEIGHT: normal; FONT-FAMILY: 'Book Antiqua'; =
mso-bidi-font-weight: bold">Code=20
Do***entation</SPAN><SPAN style=3D"FONT-FAMILY: 'Book Antiqua'"> and=20
Maintenance.</SPAN></FONT></SPAN></DIV>
<DIV align=3Djustify><FONT face=3D"Book Antiqua" =
size=3D2></FONT> </DIV>
<DIV align=3Djustify><FONT face=3D"Book Antiqua" size=3D2>Please revert =
to me at (408)=20
341 5330 if you would like to discuss this further.<BR><BR>Marketing=20
Coordinator<BR><EM><FONT color=3D#ff0000>Silicon =
Interfaces</FONT></EM><BR>a=20
software and vlsi design center<BR><BR>Email: </FONT><A=20
href=3D"mailto:info@[EMAIL PROTECTED]
"><FONT face=3D"Book Antiqua"=20
size=3D2>info@[EMAIL PROTECTED]
></A><BR><FONT face=3D"Book =
Antiqua"=20
size=3D2>Website: </FONT><A =
href=3D"http://www.siliconinterfaces.com/"><FONT=20
face=3D"Book Antiqua" size=3D2>www.siliconinterfaces.com</FONT></A><FONT =
face=3D"Book Antiqua" size=3D2> </FONT></DIV></DIV></DIV></BODY></HTML>
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