RESPONSIBILITIES
Will perform Physical Design duties, doing place-and route, which
includes: placement, scan-reordering, clock tree synthesis, in place
optimization, routing, and ECO tasks (timing, functional, noise based
ECOs). This position will also be involved in executing timing, design
rule checks, and logical vs. schematic checks for his ****tion of his
design. In addition, to his place-and-route duties, this position may
bKEYe required to execute on other parts of the design flow. Some of
these parts might include top level floor planning, top level
netlisting, timing analysis, place-and route flow development, global
design rule checks, or global logical vs. schematic checks. There will
also be flow development related to the above tasks or new tasks that
arise as technology changes. This involves flow design and
implementation via coding in various languages. In addition, strong
communication skills and an ability to work in large groups are
essential to being successful.
REQUIREMENTS
-BSEE ,MSEE preferred
-This position requires at least a Bachelor of Science or equivalent
degree with 2 years related experience or MS in Electrical engineering,
Computer engineering, engineer or an equivalent field . The level of
education is necessary in order so successfully perform the duties of
this position.
-Successful track record of delivering products to production is a
must. Including Physical Verification, Decks DRC/LVS/ERC/Antenna), Tape
out & maskview.
- placement,
- scan-reordering,
- clock tree synthesis,
- in place optimization,
- routing, and ECO tasks (timing, functional, noise based ECOs). This
position will also be involved in executing timing, design rule checks,
and logical vs. schematic checks for his ****tion of his design.
-Understanding of custom Macro blocks such as RAMs, CAMs, high-speed IO
drivers.
-Prior experience in Timing closure, clock/power Distribution and
analysis, RC Extraction and correlation, Crosstalk Analysis, IR Drop
and tapeout issues.
-Tools should include: Cadmos, Celtic, Analysis using Simplex and
Calibre
-Working knowledge of deep sub-micron routing issues as they relate to
power and timing.
-Circuit level comprehension of time critical paths. Spice experience a
plus.
-Should be a power user of Apollo/Astro for routing, PhysOpt (Physical
Compiler) for placement, PrimeTime for Timing Verification, dc_shell
etc.
- Place & route
- Tape out
|
